Study of the cross-layer architecture for guarantee of QoS in WiMAX.1. LI Jian-dong CHEN Ting DENG Shao-ping LI Chang-le. Universally composable secure Internet key exchange protocol. PENG Qing-quan PEI Qing-qi YANG Chao MA Jian-feng. Study of safety factors and non-probabilistic reliability measures of structures. Analysis of the bound performance of systematic regular RA codes in the BEC Channel SUN Rong LIU Jing-wei WANG Xin-mei MU Jian-jun. Novel short time interval measurement method WANG Hai ZHOU Wei LIU Chang-sheng WANG Shui-sheng. Iterated extended kalman particle filtering Fast calculation of the far-field scattering from the rotationally symmetric object Improved microstrip directional coupler and its application WEI Feng1 SHI Xiao-wei1 CHEN Lei2 HUANG Qiu-lin1.
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Social cooperation based multi-agent evolutionary algorithm Initialization-independent spectral clustering on the joint model ZHANG Hui-juan1 2 ZHOU Li-hua1 ZHAI Hong-ming3.Ī router queue management approach based on Nash equilibrium Star-cluster double-loop topology for the network-on-chip Low energy consumption mapping algorithm for the network-on-chip ZHANG Jianxian ZHOU Duan YANG Yintang LAI Rui GAO Xiang. YANG Yanfei ZHU Zhangming ZHOU Duan YANG Yintang.ĭelay-independent asynchronous dynamic priority arbiter for the network on chipsįat tree of Mesh(FoM): a new optical network on chip architecture Green IP lookup architecture and algorithm based on the parallel multi-pipelineĭENG Zhi GU Huaxi YANG Yintang ZENG Daibing.Īrtificial bee colony based low-energy consumption high-performance mapping in NoC High-speed low-power clock network design for NoC Low energy consumption NoC mapping algorithm based on the modified electromagnetism-like mechanism Improved shuffled frog-leaping algorithm for low-power network-on-chip mapping ZANG Mingxiang WANG Meng ZHOU Wenhong CHEN Huicang. Flexible Parallel Pipeline Network-on-chip Based on Dynamic Packet Identity Management [C]//Proceedings of the 2008 IEEE International Parallel & Distributed Processing Symposium. A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains [J].
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Journal of Tsinghua University(Science and Technology), 2008, 48(1):32-35. GALS Network-on-Chip with a Distributed-synchronous Mechanism [J]. An Asynchronous Router for Multiple Service Levels Networks on chip [C]//Proceedings of the 11 th IEEE International Symposium on Asynchronous Circuits and Systems. [2] Rostislav D, Vishnyakov V, Friedman, et al. Star-cluster Double-loop Topology for the Network-on-chip[J].